iqm.qrisp_iqm.passes.routing.core.sabre_workflow.sabre_gen_swaps#
- iqm.qrisp_iqm.passes.routing.core.sabre_workflow.sabre_gen_swaps(topology: QPUTopology, circuit_dag: CircuitDAG, greediness: int, max_instruction: float = inf, seed: int = 0, initial_phys_depth: np.ndarray = array([], dtype=int32), congestion_penalty: float = 0.0, backward_mode: bool = False, scaling_threshold: float = 0.0) tuple[list[InstructionRef], np.ndarray]#
Core SABRE routing loop.
Iteratively moves through the DAG front layer, compiling gates that are already placed on adjacent physical qubits and inserting SWAPs to bring non-adjacent operands together.
- Parameters:
topology (QPUTopology) – Hardware topology.
circuit_dag (CircuitDAG) – Circuit DAG in CSR format.
greediness (int) – Controls swap selection randomness. Higher = more deterministic.
max_instruction (float) – Only compile DAG nodes with index < max_instruction (for sectionized routing).
seed (int) – RNG seed for stochastic swap selection.
initial_phys_depth (np.ndarray) – Starting per-physical-qubit depth. The dtype is inherited from the topology (int16 on NISQ-scale devices). Non-empty when routing a section that follows a previously routed section, so depth accounting is continuous across sections.
congestion_penalty (float) – Strength of the congestion penalty applied to swap candidate scores. When > 0, swaps touching high-depth physical qubits receive a score penalty proportional to their local depth, encouraging the router to spread work across idle qubits and reduce critical-path depth. 0.0 disables the penalty (pure gate-count optimization).
backward_mode (bool) – If True, operate in backward mode (layout refinement).
scaling_threshold (float) – Instructions whose exp_depth_array weight falls below this threshold are skipped during cost-change evaluation. For deep circuits this prunes near-zero contributions from the hot loop, avoiding expensive lookups on instructions whose weight has decayed to insignificance. Default 0.0 (no skipping) for backward compatibility.
- Returns:
Compiled instructions. SWAPs have instr_index = -1.
Final logical-to-physical qubit mapping. The dtype is inherited from the topology (int16 on NISQ-scale devices).
- Return type: