transpile_to_iqm

transpile_to_iqm#

Module: iqm.qrisp_iqm.passes

iqm.qrisp_iqm.passes.transpile_to_iqm(qc: QuantumCircuit, connectivity: list[tuple[int, int]], ignore_nodes: list[int] | None = None, ignore_edges: list[tuple[int, int]] | None = None, effort: int = 100, depth_weight: float = 0.4) → QuantumCircuit#

Transpile a Qrisp QuantumCircuit for execution on IQM hardware.

This function applies the full transpilation pipeline including: - Layout and routing (SABRE-based) - SWAP optimization - Gate conversions (to CZ + PRX) - Gate cancellation and optimization

Internally delegates to create_iqm_pass_manager() and applies the resulting PassManager to the circuit.

Parameters:

  • qc (QuantumCircuit) – The Qrisp QuantumCircuit to transpile.

  • connectivity (list[list[int]]) – The connectivity describing the device topology.

  • ignore_nodes (list[int], optional) – Qubit indices to ignore (e.g., faulty qubits).

  • ignore_edges (list[tuple[int, int]], optional) – Edges to ignore in the connectivity.

  • effort (int, optional) – Effort level for layout and routing. Default is 100.

  • depth_weight (float, optional) –

    Tradeoff between gate count and circuit depth (-1.0 to 1.0).

    • -1: Circuit optimized purely for swap count.

    • 0 (default): Balanced.

    • +1: Circuit optimized purely for circuit depth.

Returns:

The transpiled circuit suitable for IQM hardware.

Return type:

QuantumCircuit

Raises:

Exception – If the circuit has more qubits than the device.

Examples

from qrisp import QuantumCircuit
from iqm.qrisp_iqm import transpile_to_iqm

# Circuit with a non-adjacent CX gate
qc = QuantumCircuit(3)
qc.h(0)
qc.cx(0, 2)
qc.measure(range(3))

# Transpile for a 4-qubit line topology
connectivity = [(0, 1), (1, 2), (2, 3)]
result = transpile_to_iqm(qc, connectivity)

print(result)

              ┌──────────────┐   ┌─┐
       qb_58: ┤ U3(π/2,-π,π) ├─■─┤M├──────────────────
              ├──────────────┤ │ └╥┘┌─────────────┐┌─┐
       qb_60: ┤ U3(π/2,-π,π) ├─■──╫─┤ U3(π/2,0,0) ├┤M├
              └──────────────┘    ║ └─────┬─┬─────┘└╥┘
       qb_59: ────────────────────╫───────┤M├───────╫─
                                  ║       └╥┘       ║
amended_qb_0: ────────────────────╫────────╫────────╫─
                                  ║        ║        ║
        cb_3: ════════════════════╩════════╩════════╩═

The non-adjacent CX(0,2) is decomposed and routed onto the line topology, resulting in a mixture of CZ and native U3 gates.

Contents